By Marwan A. Jabri
In 1984, whereas i used to be following his postgraduate direction on VLSI layout, my manager Dr. David Skellern, requested me if i used to be drawn to investigating clever methods to computerized Ie floorplanning. He advised me then: "a circuit that works regularly appears great, has a smart information and regulate stream. a quick solution to examine scholars' Ie initiatives is by way of their fioorplans.". Later, I took a path on wisdom Engineering (KE) and synthetic Intelligence (AI) with Professor John Gero, who inspired me to enquire this zone of layout automation. The assets for such improvement have been rather bad at IS&E as KE used to be a comparatively new box of analysis in Australia at the moment. \'Vhatever the problems (a solid programmmer by no means blames his instruments as David Skellern used to inform me), I undertook the research of Knowledge-Based techniques to Ie ftoor making plans as my PhD thesis topic with assistance from my manager and John Gero and the encouragement of all researchers at IS&E , who supplied an exhilarating atmosphere for my study. This quantity stories the result of my learn in the course of 1984, 1985, 1986, and 1987. The voulme bargains with Ie ftoorplanning from 4 views: floorplanning procedure, wisdom Engineering within the Ie area, the advance of knowledge-based fioorplan ning techniques and new floorplanning algorithms to be used within the total strategy.
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Additional resources for An Artificial Intelligence Approach to Integrated Circuit Floorplanning
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Separation of tasks according to knowledge involvement. Tasks will be considered algorithmic when it is possible to automate them without involving an extensive set of heuristics and when such automation offers a complete solution. The knowledge of such tasks will be considered complete. An example of an algorithmic task is the graph rectangular dualisation. The knowledge-based part contains tasks that require IC specialised knowledge to direct the search process. 1. This figure classifies the phases according to the type of the dominant problemsolving technique.
There is no way that other optima can be explored by temporarily accepting solutions that are less than optimum. This limitation led to the consideration of the statistical optimization method known as Simulated Annealing [31]. Simulated Annealing: This optimisation strategy permits the utilisation of "deteri- oration" in order to explore new optimums. 6). This optimisation strategy has since been used in different areas of VLSI CAD. The requirements of such a strategy are: 1. A concise description of a solution, 2.
These are: block layout architecture and layout design tool limitations. g. handcrafted). This knowledge involves the evaluation of both functional and physical information. 39 Functional Evaluation: Functional evaluation assumes that the design is decom- posed at the functional level, a methodology encouraged and adopted at IS&E . When judging a design on a functional basis, the distribution of neighbours on a block's periphery is evaluated according to how well they are placed to supply the functional information needed by the block.
